Hi, I’m trying out a trigger based laser alternation with Moku:Go. I get a fire pulse from the camera and there I’m looking for the falling edge to alternate.
If the file pulse stops the alternations stops also immediately but it could happen that OutputA <= LO_LVL; and OutputB <= HI_LVL; to this time point. Then the fire pulse is stopped there is an base line signal of 0 V on the analog BNC port.
Therefore I was looking for a method to set the Trigger, OutputA, and OutputB to = 0 or LO_LV
This I try to do with an break down criteria shown in the following code.
ACTIVITY: process(Clk) is
begin
if falling_edge(Clk) then
if Trigger = ‘0’ then
TriggerLowCounter <= TriggerLowCounter + 1;
else
TriggerLowCounter <= (others => ‘0’); – Reset the counter if Trigger is high
end if;
if TriggerLowCounter = RESET_THRESHOLD then
setback <= ‘1’;
OutputA <= LO_LVL;
OutputB <= LO_LVL;
TriggerLowCounter <= (others => ‘0’); – Reset the counter after setting Reset
end if;
end if;
end process;
setback <= ‘1’ is the criteria to make sure that the alternation process becomes stopped, but it worked not so well as wanted.
The current code is compiling but there are a few number of warnings.
I need a best parctice solution for reset the signals states after in activity.
In addition, the full code I use:
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
architecture Behavioural of CustomWrapper is
constant HI_LVL : signed(15 downto 0) := to_signed(32750, 16); – 5V scaled to signed 16 bits
constant LO_LVL : signed(15 downto 0) := to_signed(0, 16); – 0V scaled to signed 16 bits
constant Vref : signed(15 downto 0):= to_signed(16375, 16); – 2.5V scaled to signed 16 bits
constant RESET_THRESHOLD :integer := 10000000;
signal Step: std_logic;
signal Trigger, TriggerDly : std_logic;
signal DCLevelAddr : unsigned(6 downto 0);
signal TriggerLowCounter : unsigned(6 downto 0);
signal setback : std_logic;
begin
SCHMITT: process(Clk) is
begin
if falling_edge(Clk) then
if setback = ‘1’ then
Trigger <= ‘0’;
elsif InputA >= Vref then – Compare with the reference voltage
Trigger <= ‘1’;
elsif InputA < Vref then
Trigger <= ‘0’;
end if;
TriggerDly <= Trigger;
end if;
end process;
ACTIVITY: process(Clk) is
begin
if falling_edge(Clk) then
if Trigger = '0' then
TriggerLowCounter <= TriggerLowCounter + 1;
else
TriggerLowCounter <= (others => '0'); -- Reset the counter if Trigger is high
end if;
if TriggerLowCounter = RESET_THRESHOLD then
setback <= '1';
OutputA <= LO_LVL;
OutputB <= LO_LVL;
TriggerLowCounter <= (others => '0'); -- Reset the counter after setting Reset
end if;
end if;
end process;
-- Step the DC index on each falling edge
Step <= Trigger and not TriggerDly;
ADDR_COUNTER: process(Clk) is
begin
if falling_edge(Clk) then
if setback = '1' then
DCLevelAddr <= (others => '0');
elsif Step = '1' then -- Will wrap after 127
DCLevelAddr <= DCLevelAddr + 1;
end if;
end if;
end process;
ALTERNATION: process(Clk) is
begin
if falling_edge(Clk) then
if setback = '1' then
setback <= '0';
elsif Trigger = '1' and DCLevelAddr mod 2 = 0 then
OutputA <= HI_LVL;
OutputB <= LO_LVL;
elsif Trigger = '1' and not DCLevelAddr mod 2 = 0 then
OutputA <= LO_LVL;
OutputB <= HI_LVL;
end if;
end if;
end process;
end architecture;