Hello folks
I am monitoring an input signal using a Schmitt trigger on the falling edge. If the input signal remains constant for more than 1 sec I want to switch RESET from ‘0’ to ‘1’. To be prepared for a following measurement.
I would be glad about your ideas, to implement this function in vhdl.
Best
roflo
This is my current code to solve the problem of automated Reset.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
architecture Behavioural of CustomWrapper is
-- Constants for 5V and 0V in mV
constant HI_LVL : signed(15 downto 0) := to_signed(32750, 16); -- 5V scaled to signed 16 bits
constant LO_LVL : signed(15 downto 0) := to_signed(0, 16); -- 0V scaled to signed 16 bits
constant Vref : signed(15 downto 0):= to_signed(16375, 16); -- 2.5V scaled to signed 16 bits
constant RESET_THRESHOLD : signed(15 downto 0):= to_signed(16375, 16);
signal Step : std_logic;
signal Trigger, TriggerDly : std_logic;
signal DCLevelAddr : unsigned(6 downto 0);
signal TriggerLowCounter : unsigned(6 downto 0);
-- signal setback : unsigned(6 downto 0) := (others => '0');
begin
– Input Schmitt trigger functionality
– to help reduce trigger on noise
SCHMITT: process(Clk) is
begin
if falling_edge(Clk) then
if Reset = ‘1’ then
Trigger <= ‘0’;
elsif InputA >= Vref then – Compare with the reference voltage
Trigger <= ‘1’;
elsif InputA < Vref then
Trigger <= ‘0’;
end if;
TriggerDly <= Trigger;
end if;
end process;
process(Clk) is
begin
if falling_edge(Clk) then
if Trigger = '0' then
TriggerLowCounter <= TriggerLowCounter + 1;
else
TriggerLowCounter <= (others => '0'); -- Reset the counter if Trigger is high
end if;
if TriggerLowCounter = RESET_THRESHOLD then
Reset <= (others => '1');
TriggerLowCounter <= (others => '0'); -- Reset the counter after setting Reset
end if;
end if;
end process;
-- Step the DC index on each rising edge
Step <= Trigger and not TriggerDly;
ADDR_COUNTER: process(Clk) is
begin
if falling_edge(Clk) then
if setback = '1' then
DCLevelAddr <= (others => '0');
elsif Step = '1' then -- Will wrap after 127
DCLevelAddr <= DCLevelAddr + 1;
end if;
end if;
end process;
-- this process controlls the switching
process(Clk) is
begin
if falling_edge(Clk) then
if Trigger = '1' and DCLevelAddr mod 2 = 0 then
OutputA <= HI_LVL;
OutputB <= LO_LVL;
elsif Trigger = '1' and not DCLevelAddr mod 2 = 0 then
OutputB <= HI_LVL;
OutputA <= LO_LVL;
elsif Reset = '1' then
OutputA <= LO_LVL;
OutputB <= LO_LVL;
Reset <= (others => '0');
end if;
end if;
end process;
end architecture;
I know frome the custom wrapper introduction the Reset is normally defined as std_logic but then a pointing from ‘0’ to ‘1’ must be possible.
I found solution with running code, but there are a huge number of wanrnings I want to avoid.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
architecture Behavioural of CustomWrapper is
-- Constants for 5V and 0V in mV
constant HI_LVL : signed(15 downto 0) := to_signed(32750, 16); -- 5V scaled to signed 16 bits
constant LO_LVL : signed(15 downto 0) := to_signed(0, 16); -- 0V scaled to signed 16 bits
constant Vref : signed(15 downto 0):= to_signed(16375, 16); -- 2.5V scaled to signed 16 bits
constant RESET_THRESHOLD :integer := 10000;
signal Step: std_logic;
signal Trigger, TriggerDly : std_logic;
signal DCLevelAddr : unsigned(6 downto 0);
signal TriggerLowCounter : unsigned(6 downto 0);
signal setback : std_logic;
begin
SCHMITT: process(Clk) is
begin
if falling_edge(Clk) then
if setback = ‘1’ then
Trigger <= ‘0’;
elsif InputA >= Vref then – Compare with the reference voltage
Trigger <= ‘1’;
elsif InputA < Vref then
Trigger <= ‘0’;
end if;
TriggerDly <= Trigger;
if Trigger = ‘0’ then
TriggerLowCounter <= TriggerLowCounter + 1;
else
TriggerLowCounter <= (others => ‘0’); – Reset the counter if Trigger is high
end if;
if TriggerLowCounter = RESET_THRESHOLD then
setback <= '1';
TriggerLowCounter <= (others => '0'); -- Reset the counter after setting Reset
end if;
end if;
end process;
-- Step the DC index on each falling edge
Step <= Trigger and not TriggerDly;
ADDR_COUNTER: process(Clk) is
begin
if falling_edge(Clk) then
if setback = '1' then
DCLevelAddr <= (others => '0');
elsif Step = '1' then -- Will wrap after 127
DCLevelAddr <= DCLevelAddr + 1;
end if;
if setback = '1' then
OutputA <= LO_LVL;
OutputB <= LO_LVL;
setback <= '0';
elsif Trigger = '1' and DCLevelAddr mod 2 = 0 then
OutputA <= HI_LVL;
OutputB <= LO_LVL;
elsif Trigger = '1' and not DCLevelAddr mod 2 = 0 then
OutputB <= HI_LVL;
OutputA <= LO_LVL;
end if;
end if;
end process;
end architecture;
The warnings are the following:
WARNING: [DRC PDRC-61] SLICEM_5lutO5_C5: Dangling output pin O5 on site SLICE_X102Y42:C5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-61] SLICEM_5lutO5_C5: Dangling output pin O5 on site SLICE_X104Y37:C5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-61] SLICEM_5lutO5_C5: Dangling output pin O5 on site SLICE_X94Y60:C5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-61] SLICEM_5lutO5_C5: Dangling output pin O5 on site SLICE_X94Y65:C5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-61] SLICEM_5lutO5_C5: Dangling output pin O5 on site SLICE_X94Y75:C5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-61] SLICEM_5lutO5_C5: Dangling output pin O5 on site SLICE_X96Y60:C5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-62] SLICEM_5lutO5_B5: Dangling output pin O5 on site SLICE_X94Y45:B5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-62] SLICEM_5lutO5_B5: Dangling output pin O5 on site SLICE_X94Y60:B5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-63] SLICEM_5lutO5_A5: Dangling output pin O5 on site SLICE_X102Y42:A5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-63] SLICEM_5lutO5_A5: Dangling output pin O5 on site SLICE_X102Y43:A5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-63] SLICEM_5lutO5_A5: Dangling output pin O5 on site SLICE_X104Y44:A5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-63] SLICEM_5lutO5_A5: Dangling output pin O5 on site SLICE_X94Y45:A5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-63] SLICEM_5lutO5_A5: Dangling output pin O5 on site SLICE_X98Y69:A5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC PDRC-63] SLICEM_5lutO5_A5: Dangling output pin O5 on site SLICE_X98Y76:A5LUT. For this programming the O5 output pin should have a signal.
oWARNING: [DRC RTSTAT-10] No routable loads: 266 net(s) have no routable loads. The problem bus(es) and/or net(s) are INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][16], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][16], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][17], INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][17], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][18], INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][18], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][19], INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][19], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][20], INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][20], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][21], INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][21], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][22], INSTRS[0].INSTR_BLK.INSTR/AOut[0][Data][22], INSTRS[1].INSTR_BLK.INSTR/AOut[0][Data][23]… and (the first 15 of 220 listed).
How can I fix this in a best practice way.
Hi @roflo ,
I feel these warnings are not resolvable on your end. The MCC should be fine if it works as expected. Thanks.
Hi hanklong,
It is good to know.
But the problem I have remains. Maybe it is an understanding problem on my side when I run a Clk process.
1.) clk is the internal clock of the Moku Go box right?
If this is the case then the individual processes are run in MHz frequency or ?
so it should be possible to count the number of times in which the signal in Inputs 0 can be used as an If Else condition?
Best roflo