Hi guys, I’m in the process of building different Tigger Vairanten with the Muko: Go. And I have moved the DC_Sequencer.vhd example. My code works from the triggers point of view, but the voltage on the output channels is only 800 mV and should be 5V in HI_LVL.
Could you take a look at my code and help me further?
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
architecture Behavioural of CustomWrapper is
-- Constants for 5V and 0V in mV
constant HI_LVL : signed(15 downto 0) := to_signed(5000, 16); -- 5V in mV
constant LO_LVL : signed(15 downto 0) := to_signed(0, 16); -- 0V in mV
constant Vref : signed(15 downto 0):= to_signed(2500, 16); -- 2.5V in mV
signal Step : std_logic;
signal Trigger, TriggerDly : std_logic;
signal DCLevelAddr : unsigned(6 downto 0);
begin
– Input Schmitt trigger functionality
– to help reduce trigger on noise
SCHMITT: process(Clk) is
begin
if falling_edge(Clk) then
if Reset = ‘1’ then
Trigger <= ‘0’;
elsif InputA >= Vref then – Compare with the reference voltage
Trigger <= ‘1’;
elsif InputA < Vref then
Trigger <= ‘0’;
end if;
TriggerDly <= Trigger;
end if;
end process;
-- Step the DC index on each rising edge
Step <= Trigger and not TriggerDly;
ADDR_COUNTER: process(Clk) is
begin
if falling_edge(Clk) then
if Reset = '1' then
DCLevelAddr <= (others => '0');
elsif Step = '1' then
-- Will wrap after 127
DCLevelAddr <= DCLevelAddr + 1;
end if;
end if;
end process;
process(Clk) is
begin
if falling_edge(Clk) then
if Trigger = '1' and DCLevelAddr mod 2 = 0 then
OutputA <= HI_LVL;
OutputB <= LO_LVL;
elsif Trigger = '1' and not DCLevelAddr mod 2 = 0 then
OutputB <= HI_LVL;
OutputA <= LO_LVL;
elsif Reset = '1' then
OutputA <= LO_LVL;
OutputB <= LO_LVL;
end if;
end if;
end process;
end architecture;