I have some issue when I access the Digital Port in input mode using a MokuGo with the latest firmware release (580), while everything is fine in output mode.
To understand better, I wrote this trivial VHDL program, which simply replicates InputC(0) into OutputC(9). To feed the input I have generated a clock into OutputC(15), and externally I have wired OutputC(15) to InputC(0).
VHDL_code.png shows the code.
The MIM setup is shown in Setup_1.png and Setup_2.png (the scope in slot 1 is only a place holder)
The logic analizer data can be seen in Image_1.png and Image_2.png.
=> OutputC(9) seem totally uncorrelated to InputC(0).
Where is my fault ?