Hello, I’m getting a synthesis error when I try compiling example code from Moku’s github page. For example when I try compiling “AddSubtract_16_example.vhd“ (mcc/IP Core Templates and Examples/Adder_Subtractor) my synthesis log file is:
#-----------------------------------------------------------
Vivado v2022.2_AR000035739_AR000034905 (64-bit)
SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
Start of session at: Mon Oct 6 23:43:08 2025
Process ID: 2884341
Current directory: /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/output
Command line: vivado -log synthesis.log -nojournal -mode batch -source /deps/compile/scripts/tcl/synth.tcl -tclargs /deps/compile 40 xc7z020clg400-1 mokugo /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/src /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/lib /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores 2 3 0 4 4 5 3 2 0
Log file: /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/output/synthesis.log
Journal file:
Running On: mcc-workers-7446cfdb8d-qxtw9, OS: Linux, CPU Frequency: 4491.536 MHz, CPU Physical cores: 28, Host memory: 50485 MB
#-----------------------------------------------------------
source /deps/compile/scripts/tcl/synth.tcl
set TOP_DIR [lindex $argv 0]
set HW_VER [lindex $argv 1]
set HG_PART [lindex $argv 2]
set HG_BOARD [lindex $argv 3]
set SRC_DIR [lindex $argv 4]
set LIB_DIR [lindex $argv 5]
set IP_DCP_DIR [lindex $argv 6]
set NUM_INS [lindex $argv 7]
set NUM_OUTS [lindex $argv 8]
set NUM_MONS [lindex $argv 9]
set IN_LANES [lindex $argv 10]
set OUT_LANES [lindex $argv 11]
set NUM_SLOT_INS [lindex $argv 12]
set NUM_SLOT_OUTS [lindex $argv 13]
set NUM_CBUFS [lindex $argv 14]
set VARIANT [lindex $argv 15]
set_part $HG_PART
INFO: [Coretcl 2-1500] The part has been set to ‘xc7z020clg400-1’ for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
read_vhdl -vhdl2008 [glob $LIB_DIR/Instrument.vhd]
read_vhdl -vhdl2008 [glob $LIB_DIR/AXITypes.vhd]
read_vhdl -vhdl2008 [glob $LIB_DIR/InterlacingSupport.vhd]
read_vhdl -vhdl2008 [glob $LIB_DIR/MemoryMapSPI.vhd]
read_vhdl -vhdl2008 [glob $LIB_DIR/InstrumentCC.vhd]
read_vhdl -vhdl2008 [glob $LIB_DIR/MercurySupport.vhd]
read_vhdl -vhdl2008 [glob $LIB_DIR/MokuSupport.vhd]
set INCLUDE_ENTITY_DEFN 1
source $TOP_DIR/utilities/utilities.tcl
proc findFiles { basedir pattern } {
# Fix the directory name, this ensures the directory name is in the
# native format for the platform and contains a final directory seperator
set basedir [string trimright [file join [file normalize $basedir] { }]]
set fileList {}
# Look in the current directory for matching files, -type {f r}
# means ony readable normal files are looked at, -nocomplain stops
# an error being thrown if the returned list is empty
foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
lappend fileList $fileName
}
# Now look for any sub direcories in the current directory
foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
# Recusively call the routine on the sub directory and append any
# new files to the results
set subDirList [findFiles $dirName $pattern]
if { [llength $subDirList] > 0 } {
foreach subDirFile $subDirList {
lappend fileList $subDirFile
}
}
}
return $fileList
}
set VHDL_SRC [findFiles $SRC_DIR “*.vhd”]
if {[llength $VHDL_SRC] > 0} {
# Prevent re-definition of CustomWrapper;
# without this check, Vivado or this suite of
# scripts will not report any errors and will
# still generate the deployable bitstream.
# see Jira
foreach VHDL_FILE $VHDL_SRC {
if {[catch {exec grep -qi “entity CustomWrapper is” $VHDL_FILE} result] == 0} {
puts “Error: The entity ‘CustomWrapper’ is already defined in the library.”
exit 1
}
}
read_vhdl -vhdl2008 $VHDL_SRC
}
set VERILOG_SRC [findFiles $SRC_DIR “*.v”]
if {[llength $VERILOG_SRC] > 0} {
read_verilog $VERILOG_SRC
set_property file_type {SystemVerilog} [get_files $VERILOG_SRC]
foreach V_FILE $VERILOG_SRC {
if {[catch {exec grep -qi “module CustomWrapper” $V_FILE} result] == 0} {
set INCLUDE_ENTITY_DEFN 0
}
}
}
if {$INCLUDE_ENTITY_DEFN == 1} {
read_vhdl -vhdl2008 [glob $LIB_DIR/CustomWrapper.vhd]
}
set ip_dcps [glob -nocomplain $IP_DCP_DIR/*.dcp *.dcp]
puts $ip_dcps
/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/AddSubtract_16.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/CIC_Dec_3Ordx8.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/Cordic_Translate_16.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/Counter_32.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FFT_1024.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FFT_65536.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FIR_Filter_7coef.dcp /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/SineGen_48.dcp
foreach dcp $ip_dcps {
read_checkpoint $dcp
}
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/AddSubtract_16.dcp
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/CIC_Dec_3Ordx8.dcp
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/Cordic_Translate_16.dcp
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/Counter_32.dcp
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FFT_1024.dcp
CRITICAL WARNING: [Vivado 12-5469] The design checkpoint file ‘/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FFT_1024.dcp’ was generated for an IP by an out of context synthesis run and should not directly be used as a source in a Vivado flow. It is strongly recommended that that the original IP source file (.xci) be used.
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FFT_65536.dcp
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/FIR_Filter_7coef.dcp
Command: read_checkpoint /workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/SineGen_48.dcp
CRITICAL WARNING: [Vivado 12-5469] The design checkpoint file ‘/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/ipcores/SineGen_48.dcp’ was generated for an IP by an out of context synthesis run and should not directly be used as a source in a Vivado flow. It is strongly recommended that that the original IP source file (.xci) be used.
set_property library Moku [get_files -all -of_objects [get_filesets sources_1]]
set_property top Instrument [current_fileset]
set_property top_lib xil_defaultlib [current_fileset]
set_property top_arch Custom [current_fileset]
set_property top_file Top [current_fileset]
set_property generic “HW_VER=$HW_VER NUM_INS=$NUM_INS NUM_OUTS=$NUM_OUTS NUM_MONS=$NUM_MONS IN_LANES=$IN_LANES OUT_LANES=$OUT_LANES NUM_SLOT_INS=$NUM_SLOT_INS NUM_SLOT_OUTS=$NUM_SLOT_OUTS NUM_CBUFS=$NUM_CBUFS VARIANT=$VARIANT” [current_fileset]
synth_design -mode out_of_context -flatten_hierarchy rebuilt
Command: synth_design -mode out_of_context -flatten_hierarchy rebuilt
Starting synth_design
Using part: xc7z020clg400-1
Top: Instrument
Attempting to get a license for feature ‘Synthesis’ and/or device ‘xc7z020’
INFO: [Common 17-349] Got license for feature ‘Synthesis’ and/or device ‘xc7z020’
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 2884361
INFO: [Synth 8-11241] undeclared symbol ‘REGCCE’, assumed default net type ‘wire’ [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2457.289 ; gain = 362.781 ; free physical = 16767 ; free virtual = 43360
Synthesis current peak Physical Memory [PSS] (MB): peak = 2030.723; parent = 1773.739; children = 256.983
Synthesis current peak Virtual Memory [VSS] (MB): peak = 3427.227; parent = 2460.262; children = 966.965
CRITICAL WARNING: [Synth 8-9871] overwriting existing primary unit ‘scaleoffset2’ [/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/lib/MokuSupport.vhd:391]
WARNING: [Synth 8-9963] re-analyze unit ‘behavioral’ since unit ‘scaleoffset2’ is overwritten or removed [/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/lib/MercurySupport.vhd:932]
ERROR: [Synth 8-2716] syntax error near ‘non-printable character with the hex value ‘0xe2’’ [/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/src/Top.vhd:9]
INFO: [Synth 8-11252] unit ‘behavioural’ is ignored due to previous errors [/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/src/Top.vhd:11]
INFO: [Synth 8-10443] VHDL file ‘/workspace/03fe9b4d-20bf-4b98-b23e-8fba9d9ec368/src/Top.vhd’ is ignored due to errors
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2526.227 ; gain = 431.719 ; free physical = 16407 ; free virtual = 43196
Synthesis current peak Physical Memory [PSS] (MB): peak = 2124.219; parent = 1867.235; children = 256.983
Synthesis current peak Virtual Memory [VSS] (MB): peak = 3493.195; parent = 2526.230; children = 966.965
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
9 Infos, 1 Warnings, 1 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Mon Oct 6 23:43:27 2025…