Compiling Error

Moku Cloud Compile
1

**Moku model:Moku:Pro
**Operating system:iPadOS 16.3.1
**Software version:v2.6.1b806

Hi
I am using MATLAB HDL coder toolbox to generate a VHDL code for a simple up-counter Simulink model. I want to run this code on my Moku:Pro. However, when I compile the generated code in the Moku Cloud Compiler, I get the following error at the beginning of compiling procedure. May anybody help me find out the problem with my code? Thank you very much in advance.

Here is the error:

vivado -mode batch -notrace -source /buildbot/checkpoints/scripts/custom_instr.tcl -tclargs xczu9eg-ffvc900-2-e zynqmp 4 4 6 4 0 30 synth
h in dir /buildbot/cloudcompile/5881/output (timeout 1200 secs)
h watching logfiles {}
h argv: [b’vivado’, b’-mode’, b’batch’, b’-notrace’, b’-source’, b’/buildbot/checkpoints/scripts/custom_instr.tcl’, b’-tclargs’, b’xczu9eg-ffvc900-2-e’, b’zynqmp’, b’4’, b’4’, b’6’, b’4’, b’0’, b’30’, b’synth’]
h using PTY: False
o
o****** Vivado v2020.2 (64-bit)
o **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
o **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
o ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
o
osource /buildbot/checkpoints/scripts/custom_instr.tcl -notrace
oCommand: synth_design -mode out_of_context -flatten_hierarchy rebuilt
oStarting synth_design
oUsing part: xczu9eg-ffvc900-2-e
oTop: Instrument
oAttempting to get a license for feature ‘Synthesis’ and/or device ‘xczu9eg’
oINFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
oINFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
oINFO: [Synth 8-7075] Helper process launched with PID 58565
o---------------------------------------------------------------------------------
oStarting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2405.125 ; gain = 0.000 ; free physical = 82838 ; free virtual = 246499
o---------------------------------------------------------------------------------
eERROR: [Synth 8-2715] syntax error near has [/buildbot/cloudcompile/5881/src/UpCounter.vhd:147]
o---------------------------------------------------------------------------------
oFinished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2405.125 ; gain = 0.000 ; free physical = 83608 ; free virtual = 247269
o---------------------------------------------------------------------------------
osynthesize failed
o3 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
osynth_design failed
eERROR: [Common 17-69] Command failed: Vivado Synthesis failed
oINFO: [Common 17-206] Exiting Vivado at Fri Apr 14 15:14:56 2023…
hprogram finished with exit code 1
helapsedTime=18.508831

Here is my code:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY HDL_DUT IS
PORT( clk : IN std_logic;
reset_x : IN std_logic;
clk_enable : IN std_logic;
count_threshold : IN std_logic_vector(7 DOWNTO 0); – ufix8_En4
enable : IN std_logic;
ce_out : OUT std_logic;
out_rsvd : OUT std_logic_vector(7 DOWNTO 0) – ufix8_En4
);
END HDL_DUT;

ARCHITECTURE rtl OF HDL_DUT IS

– Signals
SIGNAL enb : std_logic;
SIGNAL switch_compare_1 : std_logic;
SIGNAL Constant_out1 : unsigned(7 DOWNTO 0); – ufix8_En7
SIGNAL count_threshold_unsigned : unsigned(7 DOWNTO 0); – ufix8_En4
SIGNAL Constant1_out1 : unsigned(7 DOWNTO 0); – uint8
SIGNAL Constant1_out1_dtc : unsigned(7 DOWNTO 0); – ufix8_En4
SIGNAL Add_out1 : unsigned(7 DOWNTO 0); – ufix8_En3
SIGNAL Add_out1_dtc : unsigned(7 DOWNTO 0); – ufix8_En4
SIGNAL Delay_out1 : unsigned(7 DOWNTO 0); – ufix8_En4
SIGNAL Add_add_cast : unsigned(15 DOWNTO 0); – ufix16_En11
SIGNAL Add_add_cast_1 : unsigned(15 DOWNTO 0); – ufix16_En11
SIGNAL Add_add_temp : unsigned(15 DOWNTO 0); – ufix16_En11
SIGNAL Relational_Operator_1_cast : unsigned(8 DOWNTO 0); – ufix9_En4
SIGNAL Relational_Operator_1_cast_1 : unsigned(8 DOWNTO 0); – ufix9_En4
SIGNAL Relational_Operator_relop1 : std_logic;
SIGNAL switch_compare_1_1 : std_logic;
SIGNAL Switch_out1 : unsigned(7 DOWNTO 0); – ufix8_En4
SIGNAL Switch1_out1 : unsigned(7 DOWNTO 0); – ufix8_En4
SIGNAL Delay1_out1 : unsigned(7 DOWNTO 0); – ufix8_En4

BEGIN

switch_compare_1 <= ‘1’ WHEN enable > ‘0’ ELSE
‘0’;

enb <= clk_enable;

Constant_out1 <= to_unsigned(16#80#, 8);

count_threshold_unsigned <= unsigned(count_threshold);

Constant1_out1 <= to_unsigned(16#00#, 8);

Constant1_out1_dtc <= Constant1_out1(3 DOWNTO 0) & ‘0’ & ‘0’ & ‘0’ & ‘0’;

Add_out1_dtc <= Add_out1(6 DOWNTO 0) & ‘0’;

Add_add_cast <= resize(Delay_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);
Add_add_cast_1 <= resize(Constant_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);
Add_add_temp <= Add_add_cast + Add_add_cast_1;
Add_out1 <= Add_add_temp(15 DOWNTO 8);

Relational_Operator_1_cast <= Add_out1 & ‘0’;
Relational_Operator_1_cast_1 <= resize(count_threshold_unsigned, 9);

Relational_Operator_relop1 <= ‘1’ WHEN Relational_Operator_1_cast > Relational_Operator_1_cast_1 ELSE
‘0’;

switch_compare_1_1 <= ‘1’ WHEN Relational_Operator_relop1 > ‘0’ ELSE
‘0’;

Switch_out1 <= Add_out1_dtc WHEN switch_compare_1_1 = ‘0’ ELSE
Constant1_out1_dtc;

Delay_process : PROCESS (clk, reset_x)
BEGIN
IF reset_x = ‘1’ THEN
Delay_out1 <= to_unsigned(16#00#, 8);
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF enb = ‘1’ THEN
Delay_out1 <= Switch1_out1;
END IF;
END IF;
END PROCESS Delay_process;

Switch1_out1 <= Delay_out1 WHEN switch_compare_1 = ‘0’ ELSE
Switch_out1;

Delay1_process : PROCESS (clk, reset_x)
BEGIN
IF reset_x = ‘1’ THEN
Delay1_out1 <= to_unsigned(16#00#, 8);
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF enb = ‘1’ THEN
Delay1_out1 <= Switch1_out1;
END IF;
END IF;
END PROCESS Delay1_process;

out_rsvd <= std_logic_vector(Delay1_out1);

ce_out <= clk_enable;

END rtl;

2

I tried running your code with a Moku:Pro FW 577 as the target and got a much different error report:

eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:9]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:12]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:18]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:21]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:22]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:23]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:24]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:25]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:26]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:27]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:28]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:29]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:30]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:31]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:32]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:35]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:36]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:37]
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:41]

I am not sure what “- ufix8_En4” is but it looks like you may be trying to comment something in line which is causing these syntax errors. The syntax for commenting is two dashes and will show the code in a slightly different color when it is commented out of the code, e.g. “-- ufix8_En4”

3

I don’t know why the “–” syntax changed to the “-” while I copied my code here. I removed all comments in my code and wrote it here again.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY HDL_DUT IS
PORT( clk : IN std_logic;
reset_x : IN std_logic;
clk_enable : IN std_logic;
count_threshold : IN std_logic_vector(7 DOWNTO 0);
enable : IN std_logic;
ce_out : OUT std_logic;
out_rsvd : OUT std_logic_vector(7 DOWNTO 0)
);
END HDL_DUT;

ARCHITECTURE rtl OF HDL_DUT IS

SIGNAL enb : std_logic;
SIGNAL switch_compare_1 : std_logic;
SIGNAL Constant_out1 : unsigned(7 DOWNTO 0);
SIGNAL count_threshold_unsigned : unsigned(7 DOWNTO 0);
SIGNAL Constant1_out1 : unsigned(7 DOWNTO 0);
SIGNAL Constant1_out1_dtc : unsigned(7 DOWNTO 0);
SIGNAL Add_out1 : unsigned(7 DOWNTO 0);
SIGNAL Add_out1_dtc : unsigned(7 DOWNTO 0);
SIGNAL Delay_out1 : unsigned(7 DOWNTO 0);
SIGNAL Add_add_cast : unsigned(15 DOWNTO 0);
SIGNAL Add_add_cast_1 : unsigned(15 DOWNTO 0);
SIGNAL Add_add_temp : unsigned(15 DOWNTO 0);
SIGNAL Relational_Operator_1_cast : unsigned(8 DOWNTO 0);
SIGNAL Relational_Operator_1_cast_1 : unsigned(8 DOWNTO 0);
SIGNAL Relational_Operator_relop1 : std_logic;
SIGNAL switch_compare_1_1 : std_logic;
SIGNAL Switch_out1 : unsigned(7 DOWNTO 0);
SIGNAL Switch1_out1 : unsigned(7 DOWNTO 0);
SIGNAL Delay1_out1 : unsigned(7 DOWNTO 0);

BEGIN

switch_compare_1 <= ‘1’ WHEN enable > ‘0’ ELSE
‘0’;

enb <= clk_enable;

Constant_out1 <= to_unsigned(16#80#, 8);

count_threshold_unsigned <= unsigned(count_threshold);

Constant1_out1 <= to_unsigned(16#00#, 8);

Constant1_out1_dtc <= Constant1_out1(3 DOWNTO 0) & ‘0’ & ‘0’ & ‘0’ & ‘0’;

Add_out1_dtc <= Add_out1(6 DOWNTO 0) & ‘0’;

Add_add_cast <= resize(Delay_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);
Add_add_cast_1 <= resize(Constant_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);
Add_add_temp <= Add_add_cast + Add_add_cast_1;
Add_out1 <= Add_add_temp(15 DOWNTO 8);

Relational_Operator_1_cast <= Add_out1 & ‘0’;
Relational_Operator_1_cast_1 <= resize(count_threshold_unsigned, 9);

Relational_Operator_relop1 <= ‘1’ WHEN Relational_Operator_1_cast > Relational_Operator_1_cast_1 ELSE
‘0’;

switch_compare_1_1 <= ‘1’ WHEN Relational_Operator_relop1 > ‘0’ ELSE
‘0’;

Switch_out1 <= Add_out1_dtc WHEN switch_compare_1_1 = ‘0’ ELSE
Constant1_out1_dtc;

Delay_process : PROCESS (clk, reset_x)
BEGIN
IF reset_x = ‘1’ THEN
Delay_out1 <= to_unsigned(16#00#, 8);
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF enb = ‘1’ THEN
Delay_out1 <= Switch1_out1;
END IF;
END IF;
END PROCESS Delay_process;

Switch1_out1 <= Delay_out1 WHEN switch_compare_1 = ‘0’ ELSE
Switch_out1;

Delay1_process : PROCESS (clk, reset_x)
BEGIN
IF reset_x = ‘1’ THEN
Delay1_out1 <= to_unsigned(16#00#, 8);
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF enb = ‘1’ THEN
Delay1_out1 <= Switch1_out1;
END IF;
END IF;
END PROCESS Delay1_process;

out_rsvd <= std_logic_vector(Delay1_out1);

ce_out <= clk_enable;

END rtl;

4

There may be some issue with copying VHDL code from the MCC browser interface to the forum since there are still quite a few syntax errors I’m getting. Regardless, I will ignore those for now and try to sort out how to fix the initial error message you sent me.

It looks like you will need to alter your entity that starts on line 5 to have some ports that match the CustomWrapper of the Moku. You may want to refer to the following resources for converting Simulink to VHDL code to be used in Moku.

Here is part one of a two part guide on how to convert Simulink to MCC.

Here is some code from our MCC documentation page that shows what the CustomWrapper ports are.