The frequency is not as expected from the values of control(1) and control(2). I would expect the FTW to be control(2)(15 to 0) & control(1), but it seems to be control(2)(15 to 0) & control(1)(15 to 0). There is no way to set the 16 MSB, giving a max frequency of 4.7kHz.
Also, is there any way to do phase modulation? It seems like it may need a re-compile of the DDS IP?
Thank you for reaching out to Liquid Instruments! I was able to replicate what you were seeing on my end. Below is the updated VHDL that you can compile and should give you the desired results. I hope this is helpful!
LIBRARY ieee;
ARCHITECTURE Behavioural OF CustomInstrument IS
SIGNAL m_axis_data_tvalid : STD_LOGIC;
SIGNAL m_axis_phase_tvalid : STD_LOGIC;
SIGNAL sine_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL m_axis_phase_tdata, freq_in : STD_LOGIC_VECTOR(47 DOWNTO 0);
BEGIN
freq_in <= (Control(2)(15 DOWNTO 0) & Control(1));
SineCosineGen : SineGen_48
PORT MAP(
aclk => clk,
-- Use the 0th bit of Control(0) to reset this module
aresetn => NOT Control(0)(0),
-- input signal is always available
s_axis_config_tvalid => '1',
-- 48-bit frequency step
s_axis_config_tdata => (freq_in),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => sine_temp,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tdata => m_axis_phase_tdata -- 48-bit phase counter output
);
-- only output data when data is valid
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF m_axis_data_tvalid THEN
-- 32-bit, the most significant 16 bits are sine
-- and the least significant 16 bits are cosine
OutputA <= signed(sine_temp(15 DOWNTO 0));
OutputB <= signed(sine_temp(31 DOWNTO 16));
END IF;
IF m_axis_phase_tvalid THEN
OutputC <= signed(m_axis_phase_tdata(47 DOWNTO 32));
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
I noticed that you also requested the ability to do phase modulation. We are currently working on adding this capability to the SineGen and I will update this thread once the files are accessible to customers on GitHub. Thank you!