# Signal Reset \<= '1' if Input A signal is constant for one second

**URL:** <https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888>\
**Category:** Moku Cloud Compile\
**Created:** [January 25, 2024, 7:54pm UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888 "2024-01-25T19:54:05Z")\
**Posts on this page:** 7\
**Page:** 1

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**Author:** ![roflo](https://avatars.discourse-cdn.com/v4/letter/r/90ced4/32.png) [@roflo](https://forum.liquidinstruments.com/u/roflo)\
**Post date:** [January 25, 2024, 7:54pm UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/1 "2024-01-25T19:54:05Z")

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Hello folks  
I am monitoring an input signal using a Schmitt trigger on the falling edge. If the input signal remains constant for more than 1 sec I want to switch RESET from ‘0’ to ‘1’. To be prepared for a following measurement.

I would be glad about your ideas, to implement this function in vhdl.

Best  
roflo

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<div class="post-metadata">

**Author:** ![roflo](https://avatars.discourse-cdn.com/v4/letter/r/90ced4/32.png) [@roflo](https://forum.liquidinstruments.com/u/roflo)\
**Post date:** [January 31, 2024, 11:22am UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/2 "2024-01-31T11:22:02Z")

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This is my current code to solve the problem of automated Reset.  
library IEEE;  
use IEEE.Std\_Logic\_1164.all;  
use IEEE.Numeric\_Std.all;

architecture Behavioural of CustomWrapper is

```
-- Constants for 5V and 0V in mV
constant HI_LVL : signed(15 downto 0) := to_signed(32750, 16); -- 5V scaled to signed 16 bits
constant LO_LVL : signed(15 downto 0) := to_signed(0, 16); -- 0V scaled to signed 16 bits
constant Vref : signed(15 downto 0):= to_signed(16375, 16); -- 2.5V scaled to signed 16 bits
constant RESET_THRESHOLD : signed(15 downto 0):= to_signed(16375, 16);

signal Step : std_logic;
signal Trigger, TriggerDly : std_logic;
signal DCLevelAddr : unsigned(6 downto 0);
signal TriggerLowCounter : unsigned(6 downto 0);
-- signal setback : unsigned(6 downto 0) := (others => '0');

```

begin  
– Input Schmitt trigger functionality  
– to help reduce trigger on noise  
SCHMITT: process(Clk) is  
begin  
if falling\_edge(Clk) then  
if Reset = ‘1’ then  
Trigger \<= ‘0’;  
elsif InputA \>= Vref then – Compare with the reference voltage  
Trigger \<= ‘1’;  
elsif InputA \< Vref then  
Trigger \<= ‘0’;  
end if;

```
        TriggerDly <= Trigger;
    end if;
end process;
      
process(Clk) is
begin
  if falling_edge(Clk) then
       if Trigger = '0' then
          TriggerLowCounter <= TriggerLowCounter + 1;
       else
           TriggerLowCounter <= (others => '0'); -- Reset the counter if Trigger is high
       end if;
  
       if TriggerLowCounter = RESET_THRESHOLD then
           Reset <= (others => '1');
          TriggerLowCounter <= (others => '0'); -- Reset the counter after setting Reset
       end if;
   end if;
end process;
        
-- Step the DC index on each rising edge
Step <= Trigger and not TriggerDly;

ADDR_COUNTER: process(Clk) is
begin
    if falling_edge(Clk) then
        if setback = '1' then
            DCLevelAddr <= (others => '0');
        elsif Step = '1' then -- Will wrap after 127
            DCLevelAddr <= DCLevelAddr + 1;
        end if;
    end if;
end process;
-- this process controlls the switching 
process(Clk) is
begin
    if falling_edge(Clk) then
        if Trigger = '1' and DCLevelAddr mod 2 = 0 then
            OutputA <= HI_LVL;
            OutputB <= LO_LVL;
        elsif Trigger = '1' and not DCLevelAddr mod 2 = 0 then 
            OutputB <= HI_LVL;
            OutputA <= LO_LVL;
        elsif Reset = '1' then
            OutputA <= LO_LVL;
            OutputB <= LO_LVL;
            Reset <= (others => '0');
        end if;
    end if;
end process;

```

end architecture;

---

<div class="post-metadata">

**Author:** ![roflo](https://avatars.discourse-cdn.com/v4/letter/r/90ced4/32.png) [@roflo](https://forum.liquidinstruments.com/u/roflo)\
**Post date:** [January 31, 2024, 11:24am UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/3 "2024-01-31T11:24:15Z")

</div>

But I get the following ERROR notice.

 ![image](https://canada1.discourse-cdn.com/flex035/uploads/liquidinstruments/original/1X/fb9d2a70fd099b6433ba19f7dfde0277a5198f50.png)  
And I need a way to fix it.

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<div class="post-metadata">

**Author:** ![roflo](https://avatars.discourse-cdn.com/v4/letter/r/90ced4/32.png) [@roflo](https://forum.liquidinstruments.com/u/roflo)\
**Post date:** [January 31, 2024, 11:29am UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/4 "2024-01-31T11:29:00Z")

</div>

I know frome the custom wrapper introduction the Reset is normally defined as std\_logic but then a pointing from ‘0’ to ‘1’ must be possible.

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<div class="post-metadata">

**Author:** ![roflo](https://avatars.discourse-cdn.com/v4/letter/r/90ced4/32.png) [@roflo](https://forum.liquidinstruments.com/u/roflo)\
**Post date:** [January 31, 2024, 1:48pm UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/5 "2024-01-31T13:48:43Z")

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I found solution with running code, but there are a huge number of wanrnings I want to avoid.

library IEEE;  
use IEEE.Std\_Logic\_1164.all;  
use IEEE.Numeric\_Std.all;

architecture Behavioural of CustomWrapper is

```
-- Constants for 5V and 0V in mV
constant HI_LVL : signed(15 downto 0) := to_signed(32750, 16); -- 5V scaled to signed 16 bits
constant LO_LVL : signed(15 downto 0) := to_signed(0, 16); -- 0V scaled to signed 16 bits
constant Vref : signed(15 downto 0):= to_signed(16375, 16); -- 2.5V scaled to signed 16 bits
constant RESET_THRESHOLD :integer := 10000;

signal Step: std_logic;
signal Trigger, TriggerDly : std_logic;
signal DCLevelAddr : unsigned(6 downto 0);
signal TriggerLowCounter : unsigned(6 downto 0);
signal setback : std_logic;

```

begin  
SCHMITT: process(Clk) is  
begin  
if falling\_edge(Clk) then  
if setback = ‘1’ then  
Trigger \<= ‘0’;  
elsif InputA \>= Vref then – Compare with the reference voltage  
Trigger \<= ‘1’;  
elsif InputA \< Vref then  
Trigger \<= ‘0’;  
end if;  
TriggerDly \<= Trigger;  
if Trigger = ‘0’ then  
TriggerLowCounter \<= TriggerLowCounter + 1;  
else  
TriggerLowCounter \<= (others =\> ‘0’); – Reset the counter if Trigger is high  
end if;

```
        if TriggerLowCounter = RESET_THRESHOLD then
             setback <= '1';
           TriggerLowCounter <= (others => '0'); -- Reset the counter after setting Reset
        end if;
   end if;
end process;
        
-- Step the DC index on each falling edge
Step <= Trigger and not TriggerDly;

ADDR_COUNTER: process(Clk) is
begin
    if falling_edge(Clk) then
        if setback = '1' then
            DCLevelAddr <= (others => '0');
        elsif Step = '1' then -- Will wrap after 127
            DCLevelAddr <= DCLevelAddr + 1;
        end if;
        if setback = '1' then
            OutputA <= LO_LVL;
            OutputB <= LO_LVL;
            setback <= '0';
        elsif Trigger = '1' and DCLevelAddr mod 2 = 0 then
            OutputA <= HI_LVL;
            OutputB <= LO_LVL;
        elsif Trigger = '1' and not DCLevelAddr mod 2 = 0 then 
            OutputB <= HI_LVL;
            OutputA <= LO_LVL;
        end if; 
    end if; 
end process;

```

end architecture;

The warnings are the following:  
WARNING: [DRC PDRC-61] SLICEM\_5lutO5\_C5: Dangling output pin O5 on site SLICE\_X102Y42:C5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-61] SLICEM\_5lutO5\_C5: Dangling output pin O5 on site SLICE\_X104Y37:C5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-61] SLICEM\_5lutO5\_C5: Dangling output pin O5 on site SLICE\_X94Y60:C5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-61] SLICEM\_5lutO5\_C5: Dangling output pin O5 on site SLICE\_X94Y65:C5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-61] SLICEM\_5lutO5\_C5: Dangling output pin O5 on site SLICE\_X94Y75:C5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-61] SLICEM\_5lutO5\_C5: Dangling output pin O5 on site SLICE\_X96Y60:C5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-62] SLICEM\_5lutO5\_B5: Dangling output pin O5 on site SLICE\_X94Y45:B5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-62] SLICEM\_5lutO5\_B5: Dangling output pin O5 on site SLICE\_X94Y60:B5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-63] SLICEM\_5lutO5\_A5: Dangling output pin O5 on site SLICE\_X102Y42:A5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-63] SLICEM\_5lutO5\_A5: Dangling output pin O5 on site SLICE\_X102Y43:A5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-63] SLICEM\_5lutO5\_A5: Dangling output pin O5 on site SLICE\_X104Y44:A5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-63] SLICEM\_5lutO5\_A5: Dangling output pin O5 on site SLICE\_X94Y45:A5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-63] SLICEM\_5lutO5\_A5: Dangling output pin O5 on site SLICE\_X98Y69:A5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC PDRC-63] SLICEM\_5lutO5\_A5: Dangling output pin O5 on site SLICE\_X98Y76:A5LUT. For this programming the O5 output pin should have a signal.  
oWARNING: [DRC RTSTAT-10] No routable loads: 266 net(s) have no routable loads. The problem bus(es) and/or net(s) are INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][16], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][16], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][17], INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][17], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][18], INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][18], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][19], INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][19], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][20], INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][20], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][21], INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][21], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][22], INSTRS[0].INSTR\_BLK.INSTR/AOut[0][Data][22], INSTRS[1].INSTR\_BLK.INSTR/AOut[0][Data][23]… and (the first 15 of 220 listed).

How can I fix this in a best practice way.

---

<div class="post-metadata">

**Author:** ![hanklong](https://yyz1.discourse-cdn.com/flex035/user_avatar/forum.liquidinstruments.com/hanklong/32/288_2.png) [@hanklong](https://forum.liquidinstruments.com/u/hanklong)\
**Post date:** [January 31, 2024, 5:33pm UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/6 "2024-01-31T17:33:04Z")

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Hi @roflo ,

I feel these warnings are not resolvable on your end. The MCC should be fine if it works as expected. Thanks.

---

<div class="post-metadata">

**Author:** ![roflo](https://avatars.discourse-cdn.com/v4/letter/r/90ced4/32.png) [@roflo](https://forum.liquidinstruments.com/u/roflo)\
**Post date:** [January 31, 2024, 7:25pm UTC](https://forum.liquidinstruments.com/t/signal-reset-1-if-input-a-signal-is-constant-for-one-second/888/7 "2024-01-31T19:25:25Z")

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Hi hanklong,

It is good to know.

But the problem I have remains. Maybe it is an understanding problem on my side when I run a Clk process.

1.) clk is the internal clock of the Moku Go box right?

1. If this is the case then the individual processes are run in MHz frequency or ?

2. so it should be possible to count the number of times in which the signal in Inputs 0 can be used as an If Else condition?

Best roflo