# Compiling Error

**URL:** <https://forum.liquidinstruments.com/t/compiling-error/691>\
**Category:** Moku Cloud Compile\
**Created:** [April 14, 2023, 3:23pm UTC](https://forum.liquidinstruments.com/t/compiling-error/691 "2023-04-14T15:23:59Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![eamini](https://avatars.discourse-cdn.com/v4/letter/e/82dd89/32.png) [@eamini](https://forum.liquidinstruments.com/u/eamini)\
**Post date:** [April 14, 2023, 3:23pm UTC](https://forum.liquidinstruments.com/t/compiling-error/691/1 "2023-04-14T15:23:59Z")

</div>

\*\*Moku model:_Moku:Pro_  
\*\*Operating system:_iPadOS 16.3.1_  
\*\*Software version:_v2.6.1b806_

Hi  
I am using MATLAB HDL coder toolbox to generate a VHDL code for a simple up-counter Simulink model. I want to run this code on my Moku:Pro. However, when I compile the generated code in the Moku Cloud Compiler, I get the following error at the beginning of compiling procedure. May anybody help me find out the problem with my code? Thank you very much in advance.

Here is the error:

vivado -mode batch -notrace -source /buildbot/checkpoints/scripts/custom\_instr.tcl -tclargs xczu9eg-ffvc900-2-e zynqmp 4 4 6 4 0 30 synth  
h in dir /buildbot/cloudcompile/5881/output (timeout 1200 secs)  
h watching logfiles {}  
h argv: [b’vivado’, b’-mode’, b’batch’, b’-notrace’, b’-source’, b’/buildbot/checkpoints/scripts/custom\_instr.tcl’, b’-tclargs’, b’xczu9eg-ffvc900-2-e’, b’zynqmp’, b’4’, b’4’, b’6’, b’4’, b’0’, b’30’, b’synth’]  
h using PTY: False  
o  
o\*\*\*\*\*\* Vivado v2020.2 (64-bit)  
o \*\*\*\* SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020  
o \*\*\*\* IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020  
o \*\* Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.  
o  
osource /buildbot/checkpoints/scripts/custom\_instr.tcl -notrace  
oCommand: synth\_design -mode out\_of\_context -flatten\_hierarchy rebuilt  
oStarting synth\_design  
oUsing part: xczu9eg-ffvc900-2-e  
oTop: Instrument  
oAttempting to get a license for feature ‘Synthesis’ and/or device ‘xczu9eg’  
oINFO: [Synth 8-7079] Multithreading enabled for synth\_design using a maximum of 4 processes.  
oINFO: [Synth 8-7078] Launching helper process for spawning children vivado processes  
oINFO: [Synth 8-7075] Helper process launched with PID 58565  
o---------------------------------------------------------------------------------  
oStarting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2405.125 ; gain = 0.000 ; free physical = 82838 ; free virtual = 246499  
o---------------------------------------------------------------------------------  
eERROR: [Synth 8-2715] syntax error near has [/buildbot/cloudcompile/5881/src/UpCounter.vhd:147]  
o---------------------------------------------------------------------------------  
oFinished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2405.125 ; gain = 0.000 ; free physical = 83608 ; free virtual = 247269  
o---------------------------------------------------------------------------------  
osynthesize failed  
o3 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.  
osynth\_design failed  
eERROR: [Common 17-69] Command failed: Vivado Synthesis failed  
oINFO: [Common 17-206] Exiting Vivado at Fri Apr 14 15:14:56 2023…  
hprogram finished with exit code 1  
helapsedTime=18.508831

Here is my code:

LIBRARY IEEE;  
USE IEEE.std\_logic\_1164.ALL;  
USE IEEE.numeric\_std.ALL;

ENTITY HDL\_DUT IS  
PORT( clk : IN std\_logic;  
reset\_x : IN std\_logic;  
clk\_enable : IN std\_logic;  
count\_threshold : IN std\_logic\_vector(7 DOWNTO 0); – ufix8\_En4  
enable : IN std\_logic;  
ce\_out : OUT std\_logic;  
out\_rsvd : OUT std\_logic\_vector(7 DOWNTO 0) – ufix8\_En4  
);  
END HDL\_DUT;

ARCHITECTURE rtl OF HDL\_DUT IS

– Signals  
SIGNAL enb : std\_logic;  
SIGNAL switch\_compare\_1 : std\_logic;  
SIGNAL Constant\_out1 : unsigned(7 DOWNTO 0); – ufix8\_En7  
SIGNAL count\_threshold\_unsigned : unsigned(7 DOWNTO 0); – ufix8\_En4  
SIGNAL Constant1\_out1 : unsigned(7 DOWNTO 0); – uint8  
SIGNAL Constant1\_out1\_dtc : unsigned(7 DOWNTO 0); – ufix8\_En4  
SIGNAL Add\_out1 : unsigned(7 DOWNTO 0); – ufix8\_En3  
SIGNAL Add\_out1\_dtc : unsigned(7 DOWNTO 0); – ufix8\_En4  
SIGNAL Delay\_out1 : unsigned(7 DOWNTO 0); – ufix8\_En4  
SIGNAL Add\_add\_cast : unsigned(15 DOWNTO 0); – ufix16\_En11  
SIGNAL Add\_add\_cast\_1 : unsigned(15 DOWNTO 0); – ufix16\_En11  
SIGNAL Add\_add\_temp : unsigned(15 DOWNTO 0); – ufix16\_En11  
SIGNAL Relational\_Operator\_1\_cast : unsigned(8 DOWNTO 0); – ufix9\_En4  
SIGNAL Relational\_Operator\_1\_cast\_1 : unsigned(8 DOWNTO 0); – ufix9\_En4  
SIGNAL Relational\_Operator\_relop1 : std\_logic;  
SIGNAL switch\_compare\_1\_1 : std\_logic;  
SIGNAL Switch\_out1 : unsigned(7 DOWNTO 0); – ufix8\_En4  
SIGNAL Switch1\_out1 : unsigned(7 DOWNTO 0); – ufix8\_En4  
SIGNAL Delay1\_out1 : unsigned(7 DOWNTO 0); – ufix8\_En4

BEGIN

switch\_compare\_1 \<= ‘1’ WHEN enable \> ‘0’ ELSE  
‘0’;

enb \<= clk\_enable;

Constant\_out1 \<= to\_unsigned(16#80#, 8);

count\_threshold\_unsigned \<= unsigned(count\_threshold);

Constant1\_out1 \<= to\_unsigned(16#00#, 8);

Constant1\_out1\_dtc \<= Constant1\_out1(3 DOWNTO 0) & ‘0’ & ‘0’ & ‘0’ & ‘0’;

Add\_out1\_dtc \<= Add\_out1(6 DOWNTO 0) & ‘0’;

Add\_add\_cast \<= resize(Delay\_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);  
Add\_add\_cast\_1 \<= resize(Constant\_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);  
Add\_add\_temp \<= Add\_add\_cast + Add\_add\_cast\_1;  
Add\_out1 \<= Add\_add\_temp(15 DOWNTO 8);

Relational\_Operator\_1\_cast \<= Add\_out1 & ‘0’;  
Relational\_Operator\_1\_cast\_1 \<= resize(count\_threshold\_unsigned, 9);

Relational\_Operator\_relop1 \<= ‘1’ WHEN Relational\_Operator\_1\_cast \> Relational\_Operator\_1\_cast\_1 ELSE  
‘0’;

switch\_compare\_1\_1 \<= ‘1’ WHEN Relational\_Operator\_relop1 \> ‘0’ ELSE  
‘0’;

Switch\_out1 \<= Add\_out1\_dtc WHEN switch\_compare\_1\_1 = ‘0’ ELSE  
Constant1\_out1\_dtc;

Delay\_process : PROCESS (clk, reset\_x)  
BEGIN  
IF reset\_x = ‘1’ THEN  
Delay\_out1 \<= to\_unsigned(16#00#, 8);  
ELSIF clk’EVENT AND clk = ‘1’ THEN  
IF enb = ‘1’ THEN  
Delay\_out1 \<= Switch1\_out1;  
END IF;  
END IF;  
END PROCESS Delay\_process;

Switch1\_out1 \<= Delay\_out1 WHEN switch\_compare\_1 = ‘0’ ELSE  
Switch\_out1;

Delay1\_process : PROCESS (clk, reset\_x)  
BEGIN  
IF reset\_x = ‘1’ THEN  
Delay1\_out1 \<= to\_unsigned(16#00#, 8);  
ELSIF clk’EVENT AND clk = ‘1’ THEN  
IF enb = ‘1’ THEN  
Delay1\_out1 \<= Switch1\_out1;  
END IF;  
END IF;  
END PROCESS Delay1\_process;

out\_rsvd \<= std\_logic\_vector(Delay1\_out1);

ce\_out \<= clk\_enable;

END rtl;

---

<div class="post-metadata">

**Author:** ![Sam.Speece](https://yyz1.discourse-cdn.com/flex035/user_avatar/forum.liquidinstruments.com/sam.speece/32/191_2.png) [@Sam.Speece](https://forum.liquidinstruments.com/u/Sam.Speece)\
**Post date:** [April 14, 2023, 5:04pm UTC](https://forum.liquidinstruments.com/t/compiling-error/691/2 "2023-04-14T17:04:37Z")

</div>

I tried running your code with a Moku:Pro FW 577 as the target and got a much different error report:

eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:9]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:12]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:18]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:21]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:22]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:23]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:24]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:25]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:26]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:27]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:28]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:29]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:30]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:31]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:32]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:35]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:36]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:37]  
eERROR: [Synth 8-2715] syntax error near � [/buildbot/cloudcompile/5884/src/Test.vhd:41]

I am not sure what “- ufix8\_En4” is but it looks like you may be trying to comment something in line which is causing these syntax errors. The syntax for commenting is two dashes and will show the code in a slightly different color when it is commented out of the code, e.g. “-- ufix8\_En4”

---

<div class="post-metadata">

**Author:** ![eamini](https://avatars.discourse-cdn.com/v4/letter/e/82dd89/32.png) [@eamini](https://forum.liquidinstruments.com/u/eamini)\
**Post date:** [April 14, 2023, 6:57pm UTC](https://forum.liquidinstruments.com/t/compiling-error/691/3 "2023-04-14T18:57:11Z")

</div>

I don’t know why the “–” syntax changed to the “-” while I copied my code here. I removed all comments in my code and wrote it here again.

LIBRARY IEEE;  
USE IEEE.std\_logic\_1164.ALL;  
USE IEEE.numeric\_std.ALL;

ENTITY HDL\_DUT IS  
PORT( clk : IN std\_logic;  
reset\_x : IN std\_logic;  
clk\_enable : IN std\_logic;  
count\_threshold : IN std\_logic\_vector(7 DOWNTO 0);  
enable : IN std\_logic;  
ce\_out : OUT std\_logic;  
out\_rsvd : OUT std\_logic\_vector(7 DOWNTO 0)  
);  
END HDL\_DUT;

ARCHITECTURE rtl OF HDL\_DUT IS

SIGNAL enb : std\_logic;  
SIGNAL switch\_compare\_1 : std\_logic;  
SIGNAL Constant\_out1 : unsigned(7 DOWNTO 0);  
SIGNAL count\_threshold\_unsigned : unsigned(7 DOWNTO 0);  
SIGNAL Constant1\_out1 : unsigned(7 DOWNTO 0);  
SIGNAL Constant1\_out1\_dtc : unsigned(7 DOWNTO 0);  
SIGNAL Add\_out1 : unsigned(7 DOWNTO 0);  
SIGNAL Add\_out1\_dtc : unsigned(7 DOWNTO 0);  
SIGNAL Delay\_out1 : unsigned(7 DOWNTO 0);  
SIGNAL Add\_add\_cast : unsigned(15 DOWNTO 0);  
SIGNAL Add\_add\_cast\_1 : unsigned(15 DOWNTO 0);  
SIGNAL Add\_add\_temp : unsigned(15 DOWNTO 0);  
SIGNAL Relational\_Operator\_1\_cast : unsigned(8 DOWNTO 0);  
SIGNAL Relational\_Operator\_1\_cast\_1 : unsigned(8 DOWNTO 0);  
SIGNAL Relational\_Operator\_relop1 : std\_logic;  
SIGNAL switch\_compare\_1\_1 : std\_logic;  
SIGNAL Switch\_out1 : unsigned(7 DOWNTO 0);  
SIGNAL Switch1\_out1 : unsigned(7 DOWNTO 0);  
SIGNAL Delay1\_out1 : unsigned(7 DOWNTO 0);

BEGIN

switch\_compare\_1 \<= ‘1’ WHEN enable \> ‘0’ ELSE  
‘0’;

enb \<= clk\_enable;

Constant\_out1 \<= to\_unsigned(16#80#, 8);

count\_threshold\_unsigned \<= unsigned(count\_threshold);

Constant1\_out1 \<= to\_unsigned(16#00#, 8);

Constant1\_out1\_dtc \<= Constant1\_out1(3 DOWNTO 0) & ‘0’ & ‘0’ & ‘0’ & ‘0’;

Add\_out1\_dtc \<= Add\_out1(6 DOWNTO 0) & ‘0’;

Add\_add\_cast \<= resize(Delay\_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);  
Add\_add\_cast\_1 \<= resize(Constant\_out1 & ‘0’ & ‘0’ & ‘0’ & ‘0’, 16);  
Add\_add\_temp \<= Add\_add\_cast + Add\_add\_cast\_1;  
Add\_out1 \<= Add\_add\_temp(15 DOWNTO 8);

Relational\_Operator\_1\_cast \<= Add\_out1 & ‘0’;  
Relational\_Operator\_1\_cast\_1 \<= resize(count\_threshold\_unsigned, 9);

Relational\_Operator\_relop1 \<= ‘1’ WHEN Relational\_Operator\_1\_cast \> Relational\_Operator\_1\_cast\_1 ELSE  
‘0’;

switch\_compare\_1\_1 \<= ‘1’ WHEN Relational\_Operator\_relop1 \> ‘0’ ELSE  
‘0’;

Switch\_out1 \<= Add\_out1\_dtc WHEN switch\_compare\_1\_1 = ‘0’ ELSE  
Constant1\_out1\_dtc;

Delay\_process : PROCESS (clk, reset\_x)  
BEGIN  
IF reset\_x = ‘1’ THEN  
Delay\_out1 \<= to\_unsigned(16#00#, 8);  
ELSIF clk’EVENT AND clk = ‘1’ THEN  
IF enb = ‘1’ THEN  
Delay\_out1 \<= Switch1\_out1;  
END IF;  
END IF;  
END PROCESS Delay\_process;

Switch1\_out1 \<= Delay\_out1 WHEN switch\_compare\_1 = ‘0’ ELSE  
Switch\_out1;

Delay1\_process : PROCESS (clk, reset\_x)  
BEGIN  
IF reset\_x = ‘1’ THEN  
Delay1\_out1 \<= to\_unsigned(16#00#, 8);  
ELSIF clk’EVENT AND clk = ‘1’ THEN  
IF enb = ‘1’ THEN  
Delay1\_out1 \<= Switch1\_out1;  
END IF;  
END IF;  
END PROCESS Delay1\_process;

out\_rsvd \<= std\_logic\_vector(Delay1\_out1);

ce\_out \<= clk\_enable;

END rtl;

---

<div class="post-metadata">

**Author:** ![Sam.Speece](https://yyz1.discourse-cdn.com/flex035/user_avatar/forum.liquidinstruments.com/sam.speece/32/191_2.png) [@Sam.Speece](https://forum.liquidinstruments.com/u/Sam.Speece)\
**Post date:** [April 14, 2023, 8:56pm UTC](https://forum.liquidinstruments.com/t/compiling-error/691/4 "2023-04-14T20:56:43Z")

</div>

There may be some issue with copying VHDL code from the MCC browser interface to the forum since there are still quite a few syntax errors I’m getting. Regardless, I will ignore those for now and try to sort out how to fix the initial error message you sent me.

It looks like you will need to alter your entity that starts on line 5 to have some ports that match the CustomWrapper of the Moku. You may want to refer to the following resources for converting Simulink to VHDL code to be used in Moku.

[Here](https://www.liquidinstruments.com/blog/2021/10/05/cloud-compile-with-mathworks-hdl-coder/) is part one of a two part guide on how to convert Simulink to MCC.

[Here](https://compile.liquidinstruments.com/#/docs/intro) is some code from our MCC documentation page that shows what the CustomWrapper ports are.