# Compiling Error 2

**URL:** <https://forum.liquidinstruments.com/t/compiling-error-2/994>\
**Category:** Moku Cloud Compile\
**Created:** [July 10, 2024, 6:49am UTC](https://forum.liquidinstruments.com/t/compiling-error-2/994 "2024-07-10T06:49:19Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![luisseo](https://avatars.discourse-cdn.com/v4/letter/l/a698b9/32.png) [@luisseo](https://forum.liquidinstruments.com/u/luisseo)\
**Post date:** [July 10, 2024, 6:49am UTC](https://forum.liquidinstruments.com/t/compiling-error-2/994/1 "2024-07-10T06:49:19Z")

</div>

I ran the example and got an error.

## VHDL example #5: PWM from analog input

– counter.vhdl

library IEEE;  
use IEEE.Std\_logic\_1164.all;  
use IEEE.Numeric\_Std.all;

–Output Strobe every 2^EXPONENT / INCREMENT Input Strobes  
–Will quantize to round integers but maintains overflow, so  
–will average out over time, but will have a ±1 cycle jitter.  
entity Counter is  
generic (  
EXPONENT : positive := 8;  
PHASE90 : boolean := false  
);  
port (  
Clk : in std\_logic;  
Reset : in std\_logic;  
Enable : in std\_logic;  
Increment : in unsigned;  
Strobe : out std\_logic  
);  
end entity;

architecture Behavioural of Counter is  
signal Count : unsigned(EXPONENT downto 0);  
begin

```
assert Increment'length <= Count'length severity FAILURE;

process(Clk) is
begin
	if rising_edge(Clk) then
		if Reset = '1' then
			Count <= (others => '0');
			if PHASE90 then
				Count(EXPONENT - 1) <= '1';
			end if;
		elsif Enable = '1' then
			--Trim the MSB but allow overflow into it.
			--This gives a single Clk cycle output pulse on Strobe.
			Count <= resize(Count(Count'left-1 downto 0), Count'length) + Increment;
		else
			Count(Count'left) <= '0';
		end if;
	end if;
end process;

Strobe <= Count(Count'left);

```

end architecture;

– pwm.vhdl  
library IEEE;  
use IEEE.Std\_Logic\_1164.all;  
use IEEE.Numeric\_Std.all;

library Moku;  
use Moku.Support.ScaleOffset;  
use Moku.Support.clip;

architecture Behavioural of CustomWrapper is  
constant HI\_LVL : signed(15 downto 0) := x"7FFF";  
constant LO\_LVL : signed(15 downto 0) := x"0000";  
signal Value: signed(12 downto 0);  
signal Count : unsigned(12 downto 0);  
signal Pulse50kHz : std\_logic;  
signal Pulse : std\_logic;  
signal OutA : std\_logic;

begin  
INPUT\_SCALE: ScaleOffset  
port map (  
Clk =\> Clk,  
Reset =\> Reset,  
X =\> InputA & “0”,  
Scale =\> signed(Control1(15 downto 0)), – For internal bus 2Vpp; setting of 0x0200 maps well  
Offset =\> signed(Control2(15 downto 0)), – For internal bus of 2Vpp, offset of 0x0400 works well for +/-1 v internal bus  
Z =\> Value,  
Valid =\> Pulse50kHz,  
OutValid =\> open  
);

```
OSC: entity WORK.Counter
    generic map (22) -- ~5 kHz from 312.5MHz
    port map (Clk, Reset, '1', to_unsigned(67, 8), Pulse50kHz);

OSC2: entity WORK.Counter
    generic map (11) --5kHz/2048 approx 10 MHz
    port map (Clk, Pulse50kHz, '1', to_unsigned(65, 9), Pulse);
  
process(Clk) is
begin
    if rising_edge(Clk) then
        if Pulse50kHz = '1' then
            Count <= resize(unsigned(clip(Value, 11, 0)), Count'length);
        elsif Pulse = '1' and Count /= 0 then
            Count <= Count - 1;
        end if;
    end if;
end process;

OutputA <= HI_LVL when Count /= 0 else LO_LVL;

```

end architecture;

\<\< Error Log \>\>  
#-----------------------------------------------------------

# Vivado v2020.2\_AR76242 (64-bit)

# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020

# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020

# Start of session at: Wed Jul 10 06:35:09 2024

# Process ID: 378016

# Current directory: /workspace/e7cb426b-f983-40d7-9c5f-471f6c93d180/output

# Command line: vivado -nojournal -mode batch -source /deps/compile/587/scripts/synth.tcl -tclargs 12 4 4 4

# Log file: /workspace/e7cb426b-f983-40d7-9c5f-471f6c93d180/output/vivado.log

# Journal file:

#-----------------------------------------------------------  
source /deps/compile/587/scripts/synth.tcl

# set TOP\_DIR $::env(TOP\_DIR)

# set HW\_VER $::env(HW\_VER)

# set HG\_PART $::env(HG\_PART)

# set HG\_BOARD $::env(HG\_BOARD)

# set SRC\_DIR $::env(SRC\_DIR)

# set adcs [lindex $argv 0]

# set dacs [lindex $argv 1]

# set cbufs [lindex $argv 2]

# set chs [lindex $argv 3]

# set\_part $HG\_PART

INFO: [Coretcl 2-1500] The part has been set to ‘xczu9eg-ffvc900-2-e’ for the current project only. Run set\_part -help for more details. To evaluate different speed grades in the current design, use the set\_speed\_grade command, or use the open\_checkpoint -part command to change the part used by an existing checkpoint design.

# read\_vhdl -vhdl2008 [glob $TOP\_DIR/lib/hdl/\*.vhd]

# read\_vhdl -vhdl2008 [glob $TOP\_DIR/src/vhdl/\*.vhd]

# read\_vhdl -vhdl2008 [glob $TOP\_DIR/lib/hdl/moku/\*.vhd] -library Moku

# if {[info exists SRC\_DIR]} {

# read\_vhdl -vhdl2008 [glob $SRC\_DIR/\*.vhd]

# }

# set ip\_dcps [glob -nocomplain $SRC\_DIR/_.dcp ip/_.dcp]

# foreach dcp $ip\_dcps {

# read\_checkpoint $dcp

# }

# set\_property top Instrument [current\_fileset]

# set\_property top\_lib xil\_defaultlib [current\_fileset]

# set\_property top\_arch Custom [current\_fileset]

# set\_property top\_file Top.vhd [current\_fileset]

# set\_property generic “HW\_VER=$HW\_VER NUM\_AIN=$adcs NUM\_AOUT=$dacs NUM\_CBUFS=$cbufs NUM\_CHANNELS=$chs” [current\_fileset]

# synth\_design -mode out\_of\_context -flatten\_hierarchy rebuilt

## Command: synth\_design -mode out\_of\_context -flatten\_hierarchy rebuilt Starting synth\_design Using part: xczu9eg-ffvc900-2-e Top: Instrument Attempting to get a license for feature ‘Synthesis’ and/or device ‘xczu9eg’ INFO: [Common 17-349] Got license for feature ‘Synthesis’ and/or device ‘xczu9eg’ INFO: [Common 17-1540] The version limit for your license is ‘2021.06’ and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Synth 8-7079] Multithreading enabled for synth\_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 378024

## Starting Synthesize : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2388.520 ; gain = 0.000 ; free physical = 43855 ; free virtual = 173470

## ERROR: [Synth 8-2396] near character ‘1’ ; 3 visible types match here [/workspace/e7cb426b-f983-40d7-9c5f-471f6c93d180/src/pwm.vhd:33] INFO: [Synth 8-1047] first match for ‘‘1’’ found here [./2008/src/standard\_2008.vhd:11] INFO: [Synth 8-1047] another match for ‘‘1’’ found here [./2008/src/standard\_2008.vhd:20] INFO: [Synth 8-1047] another match for ‘‘1’’ found here [./2008/src/std\_logic\_1164\_2008.vhd:67] ERROR: [Synth 8-2396] near character ‘1’ ; 3 visible types match here [/workspace/e7cb426b-f983-40d7-9c5f-471f6c93d180/src/pwm.vhd:37] INFO: [Synth 8-1047] first match for ‘‘1’’ found here [./2008/src/standard\_2008.vhd:11] INFO: [Synth 8-1047] another match for ‘‘1’’ found here [./2008/src/standard\_2008.vhd:20] INFO: [Synth 8-1047] another match for ‘‘1’’ found here [./2008/src/std\_logic\_1164\_2008.vhd:67] INFO: [Synth 8-2810] unit behavioural ignored due to previous errors [/workspace/e7cb426b-f983-40d7-9c5f-471f6c93d180/src/pwm.vhd:9]

## Finished Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2388.520 ; gain = 0.000 ; free physical = 44559 ; free virtual = 174174

synthesize failed  
INFO: [Common 17-83] Releasing license: Synthesis  
13 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.  
synth\_design failed  
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed  
INFO: [Common 17-206] Exiting Vivado at Wed Jul 10 06:35:16 2024…

---

<div class="post-metadata">

**Author:** ![hanklong](https://yyz1.discourse-cdn.com/flex035/user_avatar/forum.liquidinstruments.com/hanklong/32/288_2.png) [@hanklong](https://forum.liquidinstruments.com/u/hanklong)\
**Post date:** [August 14, 2024, 7:59pm UTC](https://forum.liquidinstruments.com/t/compiling-error-2/994/2 "2024-08-14T19:59:46Z")

</div>

Hi @luisseo ,

It looks like your post format is compromised. Would you mind sharing the repository link of the PWM example? I will give it a quick try.

Thanks,  
Hank