Hi Hank,
I’d tested of the FPGA Clock/integer yesterday, but that doesn’t seem to work as a fix on my end… For example, 312.5e6 / 200 = 156250.0 Hz and 312.5e6 / 30000 = 10416.666666666666 still creates the issue.
Adding more points to the waveform definitely helps. I interpolated both waveforms, and it reduces the issue but it still happens if I push the frequency further apart.
I’ve realised that the way Im going about this experiment is maybe a bit unrealistic. This morning I shifted to a clocked/triggered approach using an unused channel on an ordinary waveform generator, and it seems to resolve the experimental issue I’ve been having.
Thanks for your time and help!
Cheers,
Claude